Typically, entries in a Logical-to-Physical (L2P) address table are 4 bytes each. However, to reduce error correction code (ECC) overhead, the size of a codeword used with the media (e.g. non-volatile memory of data storage device) that stores the L2P table is typically 128 bytes or more. The codeword size results in a write amplification of 32 times or more (e.g., writing 128 bytes to the L2P table to update 4 bytes of the 128 bytes). In such a process, a 128 byte section of the L2P table is read from the media, a 4 byte subsection is modified, and the resulting 128 byte section is written back to the media. It is relatively inefficient from a performance, power, and endurance perspective to perform a 4 byte read-modify-write L2P table update for every 4 kilobyte sequential write. This challenge also arises in data centers, where it is typical for writes to be larger than 4 kilobytes, but still random from an access pattern perspective. These large granularity writes also result in the same inefficiency challenge.